Red Chili, the Chip Project Brain
The right project context for every chip-design task.
Red Chili keeps a coherent, current picture of your chip project, from spec to layout, and gives the coding agent your team already uses exactly what each task needs.
- ▸ SoC agentBoot Linux with a busybox userspace on ChiliSoC-X
- ✗ checkerA load leaves the pipeline without its data: glibc lock, user mode, virtual memory
- ◆ Red Chili · hookFeeds the core agent the load-store unit, the invariant that fired and the tests that cover it
- ● core agentPicks it up from the SoC agent and turns it into a small test: a store page fault on a copy-on-write page. Matches Spike; the checker rule is fixed
- ◆ Red Chili · hookFeeds the checks this change needs: regression, stage gate, conformance and DRAM-latency seeds
- ● verification agentThe DRAM-latency seeds catch a real D-cache bug: a line evicted while its write-back is pending. Fixed
- ◆ Red Chili · learnKeeps both lessons for every next task: an SC can end in a page fault; cache changes need DRAM-latency seeds
- ✓ Linux boots to a busybox shell · 326/326 regression · 256/256 conformance
Red Chili feeds the agent. It never drives it.
Your coding agent and its model do the reasoning, planning and writing. Red Chili feeds them the facts, checks and lessons each task needs, at the moment they need them.
A brain, not memory
Memory stores notes. A brain understands the project.
Agents and platforms already keep notes, history and retrieved text. Red Chili adds what memory alone does not.
Knowledge
Knows the structure, flows and dependencies of your project: where things are and why.
Coherence
One consistent view across spec, RTL, verification and implementation.
Maintenance
Kept current as the project changes, with stale facts caught and corrected.
Accessibility
Reachable by every engineer and agent, through the tools they already use.
Focus
Only what the current task needs, so agents spend their effort on the work.
The problem
Engineers and AI agents don’t know which project facts matter for the task in front of them.
Chip-design knowledge is spread across specs, RTL, verification, tickets, tools and people. It goes stale and stays implicit.
Rediscovery
Design and verification intent is worked out again and again, by people and agents alike.
Incoherent context
Agents edit code from scattered, stale or contradictory facts, and their output shows it.
Lost intent
Intent slips between spec, RTL and verification, so a change breaks what nobody wrote down.
The problem isn’t a lack of information.
Most teams already have too much. What’s missing is coherent, task-shaped information: what does this engineer or agent need to know for this exact task, right now?
In the agent’s loop
Four moments, fed as the agent works
Red Chili sits inside the coding agent’s own loop. At each moment it feeds what the agent needs next, and the agent decides what to do with it.
- 1
Task start
Agent
Let a load take bytes that are only partly in the store buffer, instead of replaying it
Red Chili feedsFacts
A briefing: the load-store unit’s stages, where the store buffer check runs and why, the edit boundaries and what done means
- 2
Prompt
Agent
Asks whether the check can move up to where the request is issued
Red Chili feedsLessons
The decision behind it: on the request path the check failed timing in layout, so it was registered one stage later
- 3
Edit
Agent
Changes the load-store unit and its forwarding logic
Red Chili feedsChecks
The unit’s invariant checker and its records now disagree with the RTL: update them in the same change
- 4
Commit
Agent
Gets ready to push
Red Chili feedsChecks
The checks this change needs: lint, synthesis, the stage timing gate, the regression against Spike with stall and DRAM-latency seeds, and the CoreMark floor
What the task taught is kept, so the next briefing starts sharper.
Shaped from real work on the ChillU-X1 load-store unit
One picture for every team
Current, connected and traceable
Chip projects drift: specs, RTL, test plans and layout results go out of step, and each team works from its own copy. Red Chili keeps one picture and keeps it true.
Maintained with every change
Project records are checked against the RTL and the flows on every edit and commit, so drift is caught where it starts, not found weeks later in a review.
No stale facts
Every fact carries its source, the commit or run it came from and when it was last confirmed. A result not measured since the design changed says so.
Teams in step
Design, verification and implementation read the same facts. A change to the RTL tells verification which checkers and tests it touches, and implementation which timing gates and floors it must hold.
Traceable end to end
Follow a requirement from the spec to the RTL, to the checker and tests that prove it, to the synthesis and layout results, and to the release that carries it.
Depth
From the RTL to the layout, and the project around it
Red Chili knows a chip project at the level each engineer works, in every discipline, and the plans and decisions that tie them together.
Design
- Every module: ports, parameters, users, and where each signal is declared and driven
- Hierarchy, interfaces, clocks and resets
- What each pipeline stage does, straight from the specification
- House conventions and the generators behind generated RTL
Verification
- The verification plan: every requirement with its evidence
- Checkers, tests and coverage, and which ones a change needs
- Coverage holes, known failures and past debug conclusions
- Reference-model and conformance results, run by run
Synthesis
- Area per unit, tracked across every change
- Logic depth of every pipeline stage against its budget
- Port timing budgets and the paths that break them
- Lint and synthesis results with their history
Place and route
- Every layout run: slack, clock period, utilisation and macros
- Critical paths between units, followed from run to run
- The floors no change may lose, and who approved each one
- Which results to trust: run-to-run noise and the settings behind them
The whole project
- Plans, milestones and the decisions behind them
- Releases, versions and what each block depends on
- Lessons from earlier tasks, brought back when they matter
- Every repository, from the module library to the SoC, in one picture
What focused context buys you
Better agent output
Agents work from verified facts and clear boundaries, so first attempts land closer to done.
Lower agent spend
Agents stop burning credits searching, rereading and retrying. They get the context up front and spend their budget on the task.
Faster ramp-up
Engineers start on a block with a briefing, not a week of archaeology.
Traceable by default
Every answer points to its source, from spec to regression.
Proven on our own IP
We build chips with it first
Coding agents fed by Red Chili build our own RISC-V CPUs, SoCs and an edge AI system. Here is what they built, each with its key figure.
- ChillU-SMicrocontroller CPU+24%more CoreMark per second than Ibex maxperf, in the same ORFS flow on the same binary
- ChillU-X1Application CPU3.4CoreMark/MHz at plain ‑O2, above the 3.2 published for the leading commercial cores in its class
- ChiliSoC-XApplication SoCLinuxboots to a shell on ChillU-X1, a core that passes all 256 RISC-V architectural tests against the Sail model
- ChiliSoC-SMicrocontroller SoCOpen sourceunder Apache-2.0: run it and check the work yourself
- ChiliMindEdge AI systemBit-exacta layer of a real open language model runs on the RTL, matching an independent reference
- BaseChiliSVModule libraryHundredsof verified modules, from flops to out-of-order blocks and DRAM burst engines
Built for agent-driven chip design
As chip design becomes agent-driven, Red Chili helps the engineering infrastructure evolve with it. We’re opening pilots for RTL and DV teams already using coding agents.
Request a Pilot